Since the development of integrated circuit technology, computers and computer storage devices have been made from integrated circuit chips formed from wafers of semiconductor material. After a wafer is made, the chips are typically separated from each other by dicing the wafer. Thereafter, the individual chips are bonded to carriers of various types, interconnected by wires and packaged. As technology enhancements increase, more circuits are required per chip. This is typically accomplished by (a) making the circuits smaller and (b) making the chips larger. However, there is a practical limit to both. Making chips larger requires larger field size optics, which are now at a physical limitation. Thus, increasing the density by expanding the “two dimensions” of the chips becomes prohibitive. Physical chip size limitations can be overcome by making chips as large as possible, and dividing the required circuit function into two or more chips, which are electrically connected together. However, this introduces new electrical interconnection issues.
Recently, semiconductor structures comprising three-dimensional arrays of two or more chips have emerged as an important packaging approach. A typical three-dimensional electronic module (one example of a semiconductor structure) includes multiple integrated circuit chips adhesively secured together as a monolithic structure (i.e., a “stack”). Significant attention has been directed to providing interconnections for the chips in such a multi-chip stack structure. For example, reference U.S. Pat. No. 5,567,654, which is hereby incorporated herein by reference in its entirety.
The conventional requirement for smaller component device dimensions is in direct conflict with the requirement for an increased number of interconnections between chips, because the former tends to reduce the available surface area for interconnection, while the latter demands more interconnections within the available surface area. That is, smaller component device dimensions increasingly limit the available space for interconnecting component devices, while increasing the number of connections between component devices requires more space (which is often not available) for interconnecting the component devices or a finer pitch, i.e., finer resolution, between adjacent interconnections within the available space. Unfortunately, contemporary manufacturing technology has been limited in the minimum pitch that can be used for interconnecting component devices within available space. For example, practically, the placement of component devices on circuit supporting substrates and the interconnection of those substrates becomes prone to errors as the pitch of the interconnections approaches the limit of the technology.
Thus, self-aligning electrical contacts are deemed desirable to facilitate dense electrical interconnection of two or more integrated circuit structures, such as in a multi-chip stack package.